One of the goals in power amplifier design for wireless base stations is increased efficiency. Improvements in efficiency can lead to a reduced amplifier cost (e.g. by allowing for the use of less expensive transistors with reduced power handling capability) and reduced operating expense (e.g. reduced size, reduced cooling requirements, reduced power requirements, etc.). Typically, amplifier linearity is sacrificed in order to obtain increased efficiency. Linearity is the ability of an amplifier to deliver an output signal in exact proportion (the gain factor of the amplifier) to the input signal. When linearity is sacrificed at the expense of efficiency, the output signal of the amplifier is not delivered in exact proportion to the input signal.
One technique for compensating for non-linearity in an amplifier, or any other non-linear element, is referred to as predistortion. In predistortion techniques, a non-linear distortion is applied to an input signal before the input signal is applied to the non-linear element, such that the non-linear distortion that is applied, i.e., the “predistortion”, compensates to some degree for the non-linear behaviour of the non-linear element. In order to satisfy regulatory emission requirements, the non-linearity of non-linear elements in a communications system often requires some form of linearization, as linearity often indirectly impacts one or more regulatory criterion. Accordingly, predistortion or some other linearization technique is often utilized so that regulatory emission requirements can be achieved even though linearity itself may not be an explicit or direct criterion of the regulatory emission requirement.
One predistortion technique employed today is referred to as baseband digital predistortion. In systems exhibiting “memory” (i.e., nonlinear behaviour that is a function of past inputs), a Volterra series based mechanism (or subset) is often used as a means of generating the required baseband predistortion. However, the corresponding hardware realization of the predistorter can be resource intensive.
A typical “memory polynomial” predistorter uses an actuator described by the equation:
                                          y            ⁡                          (              n              )                                =                                    ∑                              k                =                0                            K                        ⁢                                          ∑                                  q                  =                  0                                Q                            ⁢                                                φ                                      k                    ,                    q                                                  ⁢                                  x                  ⁡                                      (                                          n                      -                      q                                        )                                                  ⁢                                                                                                x                      ⁡                                              (                                                  n                          -                          q                                                )                                                                                                  k                                                                    ,                            (        1.1        )            where K and Q are implementation specific design parameters, which determine the number of branches (K+1) of the actuator and the number of previous samples or “memory” (Q+1) that are included in the predistortion compensation, respectively, and φ is a matrix of coefficients that determines the non-linear predistortion implemented by the predistorter.
Note that Eqn. 1.1 represents only a subset of the terms contained in a full Volterra series.
FIG. 1 is a block diagram of a conventional memory polynomial predistorter 100 that implements the Eqn. 1.1.
In FIG. 1, the conventional memory polynomial predistorter 100 includes K+1 branches, Branch 0 to Branch K, each having a respective FIR (Finite Impulse Response) filter, 104-0 to 104-K and a respective power term block 102-0 to 102-K, i.e., x(n),x(n)|x(n)|, x(n)|x(n)|2, . . . , x(n)|x(n)|K, in order to implement the K+1 basis functions defined by Eqn. 1.1. K dual input adders 112-0 to 112-(K−1) sum the outputs of the K+1 branches (only dual input adders 112-0 and 112-1 are shown in FIG. 1).
The FIR filter 104-0 in the first branch of the predistorter 100 is shown in detail in FIG. 1. The FIR filter 104-0 is an order Q FIR filter that includes Q delay elements 106-1 to 106-Q, Q+1 multipliers 108-0 to 108-Q and an adder 110.
In operation, a digital input x(n) is processed by each of the K+1 branches in parallel and outputs of the branches are summed by the K dual input adders 112-0 to 112-(K−1). For example, with reference to the first branch, the first branch is a power zero, or linear branch, so the power block 102-0 simply passes the input x(n) to the FIR filter 104-0 of the first branch. The Q delay elements 106-1 to 106-Q sequentially delay the output of the first power block 102-0. The input of the FIR filter 104-0 and the sequentially delayed outputs of the Q delay elements 106-1 to 106-Q are each tapped off and multiplied by a respective coefficient φ0,0 to φ0,Q using the multipliers 108-0 to 108-Q, respectively. Outputs of the multipliers 108-0 to 108-Q are summed by the adder 110 and passed to the first dual input adder 112-0.
While the adder 110 is shown as a single element in FIG. 1, in some cases the functionality of the adder 110 is realized with a plurality of adders arranged to collectively sum the outputs of the Q+1 multipliers 108-0 to 108-1. For example, in some cases the adder 110 may be realized by Q dual-input adders arranged to collectively sum the outputs of the Q+1 multipliers 108-0 to 108-Q. More generally, any number of functional elements arranged in any configuration that serves to sum the outputs of the Q+1 multipliers 108-0 to 108-Q for each sample period of the digital input signal may be used.
The power blocks 102-1 to 102-K and the FIR filters 104-1 to 104-K in the other branches operate in a similar manner to the power block 102-0 and the FIR filter 104-0 in the first branch, although the power blocks 102-1 to 102-K multiply the input signal x(n) by its magnitude raised to successively higher powers and each branch utilizes a separate set of Q+1 coefficients φk,0 to φk,Q, where k is an integer corresponding to the power to which the magnitude of the input signal x(n) is raised in the power term block for the respective branch. Accordingly, the predistorter 100 includes a total of (K+1)*(Q+1) coefficients φ0,0 to φK,Q.
In some cases the conventional actuator may be supplemented with additional “cross-terms” (i.e. constituent terms have a time difference and/or have multiple power terms) from the full Volterra series.
A traditional memory polynomial predistorter, such as the one illustrated in FIG. 1, uses “power terms” (e.g. the |x(n)|2 function included in the power term block 102-2) in each of its branches as its basis functions. The large variation in the values between the outputs of these power terms typically leads to predistorter coefficients φ with high dynamic range requirements (i.e. require a large number of bits to be able to represent both the minimum and maximum value).
An example of the output magnitudes 400, 402, 404, 406 and 408 of the basis functions of a fifth order memory polynomial predistorter, such as the memory polynomial predistorter 100 of FIG. 1, is shown in FIG. 4. The resulting coefficients when using “power term” basis functions in conventional memory polynomial predistorters typically require a large dynamic range, as demonstrated by the ratio of the magnitude of the output of the first order basis function, i.e., |x(n)|, to the magnitude of the output of the fifth order basis function, i.e., |x(n)|5, which, for example, at a normalized input magnitude of 0.25 is 0.25/0.255=256 in FIG. 4. This high ratio between the magnitudes of the outputs of the first order basis function and the fifth order basis function means that if the conventional memory polynomial predistorter is to be used to correct for a non-linearity that includes a strong fifth order component the magnitude of the Q+1 coefficients φ5,0 to φ5,Q in the fifth order branch of the predistorter are large, i.e. the coefficients potentially have a large dynamic range requiring a large number of bits, in order to weight the output of the fifth order power term block 102-4 (not explicitly shown in FIG. 1) so that the magnitude of the fifth order predistortion output of the filter 104-4 (not explicitly shown in FIG. 1) in the fifth order branch of the predistorter is sufficiently large enough to provide the desired fifth order predistortion.
The large number of bits required to be able to represent both the minimum and maximum value of the outputs of the power term blocks 102-0 to 102-K and the coefficients φ0,0 to φK,Q in the branches of the predistorter actuator 100 leads to increased computational cost in the corresponding hardware realization of the constituent arithmetic units (e.g. multipliers 108-0 to 108-Q, adders 110 and 112-0 to 112-(K−1), accumulators (not shown)). However, simply reducing the number of bits used through, for example, direct quantization may result in reduced system performance since the accuracy of the predistortion may be reduced by the direct quantization.
In an attempt to improve the performance of conventional memory correction predistortion systems, in some prior art systems multiple sets of coefficients φ have been defined, with each distinct set of coefficients referred to as a “section”. The bounds of the operating region of each section correspond to values of the magnitude of the input signal. For example, the section number φ may be determined in accordance withlowerSecVal(φ)≦|x(n)|<upperSecVal(φ),  (1.2)where lowerSecVal and upperSecVal are vectors that define the lower and upper bounds of each section, respectively. A possible realization of a predistortion actuator 200 that implements this conventional sectioning scheme is shown schematically in FIG. 2.
The predistortion actuator 200 shown in FIG. 2 includes a magnitude detector 202, a section determination block 206, a plurality of K+1 branches, branch 0 to branch K, and a plurality of K adders, 212-0 to 212-(K−1). Each branch includes a respective FIR Filter 210-0 to 210-K. In FIG. 2, the FIR filters 210-0 to 210-K are each implemented as an order Q FIR filter, which means that each FIR filter 210-0 to 210-K includes Q+1 taps. Branches 1 to K each include a respective multiplier 208-1 to 208-K. Branches 2 to K each further include a respective power term block 204-1 to 204-(K−1).
The magnitude detector 202 is connected to an input of the predistortion actuator to receive a predistorter input signal x(n). The predistorter input also provides the predistorter input signal x(n) to the FIR Filter 210-0 in branch 0 and to each of the K multipliers 208-1 to 208-K. The magnitude detector 202 provides a magnitude output |x(n)| corresponding to the magnitude of the predistorter input signal x(n) to the multiplier 208-1 in branch 1 and to each of the power term blocks 204-1 to 204-(K−1) in branches 2 to K, respectively. The respective power term block 204-1 to 204-(K−1) of branches 2 to K respectively raise the magnitude output |x(n)| they receive from the magnitude detector 202 to successively higher orders of power corresponding to their respective branch number, i.e. the power term block 204-1 in branch 2 squares the magnitude signal |x(n)| it receives from the magnitude detector 202. The respective outputs of the power term blocks 204-1 to 204-(K−1) are provided to multipliers 208-2 to 208-K. The K multipliers 208-1 to 208-K multiply their respective inputs together and provide the respective multiplied results to the FIR Filters 210-1 to 210-K. The plurality of K adders 212-0 to 212-(K−1) sum the outputs of the K+1 FIR Filters 210-0 to 210-K to produce a predistorted output signal y(n).
The section determination block 206 monitors the magnitude output |x(n)| of the magnitude detector 202 to determine which section number φ the current input sample belongs to according to Eqn. 1.2, and adjusts branch coefficients φ0,0 to φK,Q in the K+1 FIR Filters 210-0 to 210-K of each branch of the actuator according to the determined section number φ.
In this way, the coefficients of the constituent FIR filters 210-0 to 210-K may be changed at each sample period n responsive to the instantaneous magnitude of the input signal x(n).
A graphical example of how coefficient sectioning sub-divides the predistortion characteristic is given in FIG. 3. FIG. 3 is a plot of output envelope amplitude versus input envelope amplitude for a predistortion actuator using a sectioning scheme where the input envelope amplitude is sectioned into a plurality of 15 sections 300-1 to 300-15 respectively representing an input envelope value range, such as the one defined in Eqn. 1.2.
The use of coefficient sectioning in a predistortion actuator has a number of impacts on a memory correction predistortion system incorporating the predistortion actuator. Examples of those impacts may include:
1. the predistortion actuator must be capable of completely changing its coefficient values every input sample period according to the predetermined criteria (e.g. input envelope amplitude);
2. additional logic is required to determine which section corresponds to the input envelope amplitude of a current input sample of the input signal x(n);
3. additional memory storage is required for each section, as training is required to generate coefficients for each section to generate the desired predistortion; and
4. the training algorithm must be applied to each section, thereby increasing the overall computational requirement for the training algorithm.
While coefficient sectioning typically provides a performance improvement over global, i.e., non-sectioned, coefficient polynomial memory correction predistorters, the performance improvement comes with a further increase in hardware and computational costs.